The present invention relates to a testing technique for a semiconductor device. More particularly, it relates to a method, a device and a system for testing in which a test pattern for inspection is prepared based on trace data in the operating state of the semiconductor device mounted on implemented equipment, and to software therefor.
In characterization tests for a semiconductor device, which are conducted in the course of research and development, a series of comprehensive tests are carried out. These include tests such as various operational margin tests with varying power or timing, in addition to DC parametric tests, functional tests or AC parametric tests for semiconductor devices. For example, high-performance automatic testing equipment (ATE) using sampling data prescribing operational specifications for semiconductor devices can be used.
In the manufacturing process for a semiconductor device, a mass production test, also termed a final test, is carried out on a packaged semiconductor device following a wafer test and dicing and bonding steps to guarantee that the semiconductor device meets minimum electrical specifications. Usually, on a device under test (DUT), continuity and leakage tests, basic functional tests, DC parametric tests and, as necessary, minimum margin tests are performed using a low-cost automatic testing device for mass production. The automatic testing equipment is connected to an auto-handler which sorts the devices tested according to classes and grades (or categories) based on test results.
In this final test, shorter test time is of paramount importance, so that test items and test patterns selected as necessary minimum items may be used in testing without performing comprehensive tests.
However, there are occasions in which a semiconductor device product, verified to be good in the final test stage and marketed, suffers from malfunctions when mounted and operated on electronic equipment.
In other words, the final test is usually conducted using low-cost automatic testing equipment. Hence, there is a limit to the pattern length of a test pattern (test vector length) or the number of different patterns for functional tests. For example, a device failure undetectable with a test pattern used in a final test is sometimes detected by haphazard after product shipment.
With recent progress in device miniaturization, leading to high integration and high functionality, the number of gates mounted on a single chip is drastically increased. The increased logical complexities of these chips make it more and more difficult to provide test patterns capable of detecting all of the defects dependent on combinations of input/output patterns of the logical integrated circuits. In the case of a program-controlled logic IC, particularly, the combination of input/output patterns to the logical IC is varied depending on the contents, the operating (running) states, or the haphazard phenomenon. Thus, in reality it is almost impossible to provide all of these combinations for testing logical ICs at the outset.
Several methods are currently employed for generating a test pattern for use in automatic testing equipment that tests semiconductor devices. Among these methods, one method uses a tool for converting the simulated result obtained by a logical simulator used in designing a semiconductor device into a test pattern for conversion to a test pattern for automatic testing equipment in question. Another method uses an automatic pattern generating tool (APG). A third method generates a test pattern and uses a failure simulator taking into account the rate of failure detection. These methods generate test patterns based on simulation.
As another method, a test pattern is acquired by using a real device. As a typical time-honored technique, a previously provided input pattern (random pattern) is applied to a Known Good Device (KGD) to sample an output from the KGD. The sampled output as a pattern of expected values is synthesized with an input pattern to generate a test vector.
There is another device for generating a test pattern that acquires a signal waveform in the course of the operation with the semiconductor integrated device mounted on implemented equipment. As described in JP Patent Kokai JP-A-7-306245, a well-known method involves sampling a terminal waveform of a semiconductor integrated device mounted on implemented equipment, appending the input/output information input by a manufacturer of the implemented equipment as to the terminal waveform, using a waveform editor of testing equipment, and acquiring a test pattern for inspection from the resulting data. In this method, the pattern quality is appreciably influenced by whether the input/output information acquired from the manufacturer of the implemented equipment is the correct information. The above-mentioned JP Patent Kokai JP-A-7-306245 proposes a testing method comprising: pattern generating means made up of a data conversion circuit for acquiring the signal waveform data at the time of operation at the terminal of an LSI under test by a logic analyzer and converting the data into an input pattern for testing, and a data memory for storing an input pattern output by the data conversion circuit; a voltage setting means for setting a variety of voltages, inclusive of a source voltage VDD, a high level input voltage VIH, a low level input voltage VIL, and a grounding voltage, for providing a difference in input and output current values produced by the driving input of a preset input pattern and supplying the so-set voltages to the LSI; and an input/output information holding means for receiving an input pattern output by pattern generating means for applying the input pattern received to a specified terminal designated for current measurement to measure the input and output currents produced in the specified terminal designated for current measurement to measure the input and output currents produced in the specified terminal, detecting the difference between the input and output currents, verifying PASS/FAIL in the input pattern and extracting and holding the FAIL information. The input pattern for testing, generated by the pattern generating means, is synthesized with the FAIL information output by the input/output information holding means, to generate a test pattern for inspection corresponding to the LSI. The entire disclosure of JP-A-7-306245 is herein incorporated by reference.
However, various problems have been encountered during investigations toward the present invention. Namely, in the current state of the art, there is provided no tool for reflecting the malfunction information pertinent to the semiconductor device products when a test pattern of testing equipment is used during a run on implemented equipment.
If malfunction or failures (flaws) occur on the implemented equipment, and the semiconductor device product is responsible for the failure, the semiconductor device product is exchanged with a KGD, by way of a repair service to check whether or not the implemented equipment operates normally. If, as a result of such exchange, the implemented equipment operates normally, the result is acceptable to a user. However, there are occasions on which the malfunction is not resolved even by exchange with a KGD. For example, if the semiconductor device is a program-controlled CPU or a peripheral device, memory device etc., adapted for exchanging data with a program-controlled CPU, the input/output pattern or the timing might change, thereby producing a malfunction as a result of the failure of a device with respect to a certain combination of randomly occurring pattern sequences due to changes in the input/output pattern or timing depending on the operating states or programs executed on the CPU.
Even if, in such a case, the semiconductor device is exchanged for a KGD and mounted on the implemented equipment, the KGD may undergo malfunction for such a specific pattern combination.
If the malfunction of the semiconductor device is not resolved, such that the manufacturer has to recover the products, considerable loss is incurred. On the other hand, it takes considerable labor and operating steps to analyze the defects of the semiconductor device to produce a test pattern having a pattern sequence for detecting the specific malfunction.
It is therefore an object of the present invention to provide a method, apparatus and program product for generating a test pattern enabling detection of malfunction on mounting on implemented equipment in advance, such as at the time of production tests. Other objects, advantages and features of the present invention will be apparent from the entire description of the present invention and the claims.
According to a first aspect of the present invention, there is provided a method for testing a semiconductor device comprising the steps of:
a first step of acquiring signal waveform data for a time period beginning with a first time point going back from occurrence time of a malfunction of a first semiconductor device and running to a second time point inclusive of the malfunctioning time of the semiconductor device, in connection with a preset terminal signal of the semiconductor device;
a second step of generating a test pattern usable in an automatic testing device adapted for testing the semiconductor device as a device to be measured, from the acquired signal waveform data, the test pattern comprising data for the malfunctioning time changed into normal data; and
a third step of testing a semiconductor device of a same series of production as the first semiconductor device, as a semiconductor device under test, using the so-generated test pattern in the automatic testing device.
In the first step of the above-described method, the implemented equipment carrying the semiconductor device is run in operation and signal waveform data of a preset group of terminals of the semiconductor device is acquired using a logical analyzer employing a preset failure signal indicating the malfunction of the semiconductor device as a trigger.
In the second step of the above-described method, as data for the malfunctioning time is changed into normal data to prepare a pattern of expected values for an output signal of the semiconductor device, it is checked whether or not setting of an input signal to the semiconductor device is present in the test pattern. If the setting is not present in the test pattern, a test pattern for setting the input signal to the semiconductor device is automatically inserted.
According to a second aspect of the present invention, there is provided a system for testing a semiconductor device. The system comprises:
an acquiring unit acquiring signal waveform data for a time period beginning with a first time point going back from occurrence time of a malfunction of a first semiconductor device and running to a second time point inclusive of the malfunctioning time of semiconductor device, in connection with a signal at a preset terminal of the semiconductor device; and
a generator unit generating a test pattern usable in an automatic testing device adapted for testing the semiconductor device as a device under test, from the acquired signal waveform data, the test pattern comprising data for the malfunctioning time changed into normal data;
wherein in the automatic testing device, a semiconductor device of a same series of production as the first semiconductor device, as a semiconductor device to be measured, is tested using the so-generated test pattern.
According to a third aspect of the present invention, a mass production tester conducts a test on a semiconductor device (or devices), which is of the same series (type) of production as a semiconductor device product, using a test pattern or a test program output by a pattern generating device adapted for automatically converting the signal waveform data at the time of occurrence of defects in the semiconductor device products mounted on an implemented equipment into a test pattern or program for inspecting the semiconductor device.
According to a fourth aspect of the present invention, there is provided a pattern generating device. In the pattern generating device, signal waveform data from means for acquiring signal waveform data for a time period beginning with a first time point going back from the time of occurrence of a malfunction of a semiconductor device and running until a second time point inclusive of the malfunctioning time of the semiconductor device, is input in connection with a terminal signal of the semiconductor device. A test pattern usable in an automatic testing equipment adapted for testing the semiconductor device as a device under test is acquired from the acquired signal waveform data, with the test pattern comprising data for the malfunctioning time changed into normal data. The data for the malfunctioning time is changed to normal data to generate a pattern of expected values for the output signals of the semiconductor device. If the setting required in association with the output signal of the semiconductor device is not present in the test pattern, an input signal to the semiconductor device is set by an input signal setting unit.
According to a 5th aspect of the present invention, there is provided a method for generating a test pattern comprising:
acquiring signal waveform data for a time period beginning from a first time point going back from occurrence of a malfunction of a first semiconductor device and running to a second time point inclusive of a malfunctioning time of the semiconductor device, in connection with a signal at a preset terminal of the semiconductor device; and
preparing a test pattern usable in an automatic testing device adapted for testing the semiconductor device as a device under test, from the acquired signal waveform data, the test pattern comprising data for the malfunctioning time changed into normal data;
wherein data for malfunction is changed into normal data to prepare a pattern of expected values for an output signal of the semiconductor device, it is checked whether or not setting of an input signal required in association with the output signal of the semiconductor device is present in the signal waveform pattern, provided that if the setting is not present in the test pattern, a test pattern for setting the input signal to the semiconductor device is automatically inserted.
According to a 6th aspect of the present invention, there is provided a computer readable program product for performing the steps of the method. The program product may be carried on any carrier, which may be a hard, soft or dynamic carrier such as diskette, CD, memory, or carrier wave, or else whatever that may carry the program product.
Other aspects and features are also mentioned in the appended claims, the entire disclosure thereof being incorporated therein by reference thereto.